The present invention relates generally to crystal growing apparatus used in growing monocrystalline silicon ingots, and more particularly to a control assembly for use in such a crystal growing apparatus. Single crystal silicon, which is the starting material for most semiconductor electronic component fabrication, is commonly prepared by the so-called Czochralski (“Cz”) method. Conventional growth of the crystal is most commonly carried out in a crystal pulling furnace. In this method, polycrystalline silicon (“polysilicon”) is charged to a crucible and melted by a heater surrounding the outer surface of the crucible side wall. A seed crystal is brought into contact with the molten silicon and a single crystal ingot is grown by relatively slow extraction via a crystal puller. After formation of a neck is complete, the diameter of the crystal ingot is enlarged by decreasing the pulling rate and/or the melt temperature until the desired or target diameter is reached. The cylindrical main body of the crystal, which preferably has an approximately constant diameter, is then grown by controlling the pull rate and the melt temperature while compensating for the decreasing melt level. Near the end of the growth process, the crystal diameter must be reduced gradually to form an end-cone. Typically, the end-cone is formed by increasing the pull rate and heat supplied to the crucible. When the diameter becomes small enough, the ingot is then separated from the melt.
It is now recognized that a number of defects in single crystal silicon form in the growth chamber as the post growth ingot cools from the temperature of solidification. More specifically, intrinsic point defects, such as crystal lattice vacancies or silicon self-interstitials, remain soluble in the silicon lattice while the temperature of the ingot remains above a threshold temperature. After the ingot cools below the threshold temperature, the given concentration of intrinsic point defects becomes critically supersaturated. Upon cooling to below this threshold temperature, a reaction or agglomeration event occurs, resulting in the formation of agglomerated intrinsic point defects, which can produces other defects such as edge slips.
The type and initial concentration of these point defects in the silicon are determined as the ingot cools from the temperature of solidification (i.e., about 1410° C.) to a temperature greater than about 1300° C.; that is, the type and initial concentration of these defects are controlled by the ratio v/G0, where v is the growth velocity and G0 is the average axial temperature gradient over this temperature range. Accordingly, process conditions, such as growth rate (which affect v), as well as hot zone configurations (which affect G0), can be controlled to determine whether the intrinsic point defects within the single crystal silicon will be predominantly vacancies (where v/G0 is generally greater than the critical value) or self-interstitials (where v/G0 is generally less than the critical value).
Defects associated with the agglomeration of crystal lattice vacancies, or vacancy intrinsic point defects, include such observable crystal defects as D-defects, Flow Pattern Defects (FPDs), Gate Oxide Integrity (GOI) Defects, Crystal Originated Particle (COP) Defects, and crystal originated Light Point Defects (LPDs), as well as certain classes of bulk defects observed by infrared light scattering techniques (such as Scanning Infrared Microscopy and Laser Scanning Tomography).
Defects which act as the nuclei for the formation of oxidation induced stacking faults (OISF), are also present in regions of excess vacancies, or regions where some concentration of free vacancies are present but where agglomeration has not occurred. It is speculated that this particular defect, generally formed proximate the boundary between interstitial and vacancy (V/I boundary) dominated material, is a high temperature nucleated oxygen precipitate catalyzed by the presence of excess vacancies; that is, it is speculated that this defect results from an interaction between oxygen and “free” vacancies in a region near the V/I boundary.
Defects relating to self-interstitials are less well studied. They are generally regarded as being low densities of interstitial-type dislocation loops or networks. Such defects are not responsible for gate oxide integrity failures, an important wafer performance criterion, but they are widely recognized to be the cause of other types of device failures usually associated with current leakage problems.
Agglomerated defect formation generally occurs in two steps. First, defect “nucleation” occurs, which is the result of the intrinsic point defects being supersaturated at a given temperature. Once this “nucleation threshold” temperature is reached, intrinsic point defects agglomerate. The intrinsic point defects will continue to diffuse through the silicon lattice as long as the temperature of the portion of the ingot in which they are present remains above a second threshold temperature (i.e., a “diffusivity threshold”). Below the second threshold temperature, intrinsic point defects are no longer mobile within commercially practical periods of time. While the ingot remains above this temperature, vacancy or interstitial intrinsic point defects diffuse through the crystal lattice to sites where agglomerated vacancy defects or interstitial defects, respectively, are already present, causing a given agglomerated defect to grow in size. Growth occurs because these agglomerated defect sites essentially act as “sinks,” attracting and collecting intrinsic point defects because of the more favorable energy state of the agglomeration.
Accordingly, the formation and size of agglomerated defects are dependent upon the growth conditions, including v/G0 (which impacts the initial concentration of such point defects), as well as the cooling rate or residence time of the main body of the ingot over the range of temperatures bound by the “nucleation threshold” at the upper end and the “diffusivity threshold” (which impacts the size and density of such defects) at the lower end. Thus, control of the cooling rate or residence time enables the formation of agglomerated intrinsic point defects to be suppressed over much larger ranges of values for v/G0; that is, controlled cooling allows for a much larger “window” of acceptable v/G0 values to be employed while still enabling the growth of substantially defect-free silicon. Reducing the quenching rate too severely can compromise process robustness in production. For example, production yield loss has been identified to be caused by insufficient cooling.
Under certain thermal conditions (for example, those present when “quench” cooling is employed), slip dislocations are known to form at the lateral or radial edge of the ingot. Slip dislocations can also occur at locations radially inward of the edge in a region (when present) wherein vacancies are the predominant intrinsic point defect. Without being held to any particular theory, it generally believed that the formation of such dislocations are, at least in part, due to thermal stress which occurs in the ingot as it cools from the solidification temperature. Edge slip dislocations typically form and propagate along the <110> interface between <111> planes. It is believed these form as a result of a radial temperature gradient that is too large; that is, an outer region of the ingot, proximate the radial edge, cools much faster than an inner region of the ingot. In such instances, silicon in this outer region contacts around the hotter, and thus expanded, inner region. This contractions generates internal stress, both tensile stress (at or near the surface of the ingot) and compressive stress (at or near the center of the ingot). In the case of edge slip, tensile stress dominates. If this stress is above the critical resolve shear stress at a given temperature (critical resolve shear stress being a function of temperature), a slip dislocation at or proximate the edge occurs. Although the axial temperature gradient can be a factor, experience to-date suggests edge slip dislocations are primarily a function of the radial gradient of a given segment of the ingot upon entry and/or exist of an upper heater.
As an example, one crystal puller used for controlling the cooling of monocrystalline ingots above the nucleation threshold of intrinsic point defects includes an electrical resistance heater mounted in the pull chamber of the crystal puller housing generally toward the bottom of the pull chamber of the housing. The electrical resistance heater has heating segments that may be constructed of equal length (e.g., a non-profiled heater) or of stepped, or staggered lengths (e.g., a profiled heater). As portions of the ingot grown in the puller are pulled upward into radial registration with the heater, heat is radiated by the heater to these portions of the ingot to reduce the cooling rate of the ingot. Commonly assigned U.S. Pat. No. 6,503,322, the entire disclosure of which is incorporated herein by reference, describes an electrical resistance heater for use in a crystal puller to facilitate reduction of agglomeration of intrinsic point defects.
Commonly assigned U.S. patent application Ser. No. 09/661,745, the entire disclosure of which is incorporated herein by reference, discloses a quenching process for growing a monocrystalline silicon ingot according to the Czochralski method in which the nucleation and/or growth of interstitial type defects is suppressed by controlling the cooling rate of the ingot through nucleation. For example, initial growth conditions may be selected to provide an ingot containing silicon self-interstitials as the predominant intrinsic point defect from the center to the edge of the ingot, or a central core in which vacancies are the predominant intrinsic point defect surrounded by an axially symmetric region in which silicon self-interstitials are the predominant intrinsic point defect. As the ingot cools while being pulled upward within the crystal puller, the temperature of the ingot is maintained above the temperature range at which nucleation of the self-interstitials occurs, such as about 850° C.–950° C., for a time period sufficient for adequate diffusion of intrinsic point defects. Then, the ingot is rapidly cooled, or quenched, through the nucleation temperature range to inhibit nucleation. Below the nucleation temperature range, no further nucleation will occur. The process is disclosed as producing ingots that are substantially free of intrinsic point defects.
Other methods for controlling the cooling rate of a post growth ingot include pulling the ingot away from the melt and upward within the crystal puller at pre-programmed pull out rates. However, pulling the post growth ingot according to a predetermined fixed rate does not allow adjustments for temperature variations, which frequently occur during post growth cooling stages in almost all of the crystal processes.
While the crystal puller configurations discussed above are effective for increasing the dwell time of the ingot above a desired temperature, further improvements are desired for carrying out the quenching process described above to produce ingots that are substantially free of intrinsic point defects and edge slips. In particular, improvements are desired for adjusting post-growth process parameters in response to actual cooling rates captured during processing.